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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. HM66AEB36104/HM66AEB18204 HM66AEB9404 36-Mbit DDR II SRAM 4-word Burst ADE-203-1368 (Z) Preliminary Rev. 0.0 Jan. 27, 2003 Description The HM66AEB36104 is a 1,048,576-word by 36-bit, the HM66AEB18204 is a 2,097,152-word by 18-bit, and the HM66AEB9404 is a 4,194,304-word by 9-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and K) and are latched on the positive edge of K and K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package. Preliminary: The specifications of this device are subject to change without notice. Please contact your nearest Hitachi's Sales Dept. regarding specifications. HM66AEB36104/18204/9404 Features * 1.8 V 0.1 V power supply for core (VDD) * 1.4 V to VDD power supply for I/O (VDDQ) * DLL circuitry for wide output data valid window and future frequency scaling * Pipelined double data rate operation * Common data input/output bus * Four-tick burst for reduced address frequency * Two input clocks (K and K) for precise DDR timing at clock rising edges only * Two output clocks (C and C) for precise flight time and clock skew matching-clock and data delivered together to receiving device * Internally self-timed write control * Clock-stop capability with s restart * User programmable impedance output * Fast clock cycle time: 3.0 ns (333 MHz)/3.3 ns (300 MHz)/4.0 ns (250 MHz)/ 5.0 ns (200 MHz)/6.0 ns (167 MHz) * Simple control logic for easy depth expansion * JTAG boundary scan Ordering Information Type No. HM66AEB36104BP-30 HM66AEB36104BP-33 HM66AEB36104BP-40 HM66AEB36104BP-50 HM66AEB36104BP-60 HM66AEB18204BP-30 HM66AEB18204BP-33 HM66AEB18204BP-40 HM66AEB18204BP-50 HM66AEB18204BP-60 HM66AEB9404BP-30 HM66AEB9404BP-33 HM66AEB9404BP-40 HM66AEB9404BP-50 HM66AEB9404BP-60 Organization 1-M word x 36-bit Cycle time 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns Clock frequency 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Package Plastic FBGA 165-pin (BP-165A) 2-M word x 18-bit 4-M word x 9-bit Rev.0.0, Jan. 2003, page 2 of 30 HM66AEB36104/18204/9404 Pin Arrangement (HM66AEB36104) 165PIN-BGA 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS DQ27 NC DQ29 NC DQ30 DQ31 VREF NC NC DQ33 NC DQ35 NC TCK 3 SA DQ18 DQ28 DQ19 DQ20 DQ21 DQ22 VDDQ DQ32 DQ23 DQ24 DQ34 DQ25 DQ26 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW2 BW3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 BW1 BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 NC NC DQ17 NC DQ15 NC NC VREF DQ13 DQ12 NC DQ11 NC DQ9 TMS 11 CQ DQ8 DQ7 DQ16 DQ6 DQ5 DQ14 ZQ DQ4 DQ3 DQ2 DQ1 DQ10 DQ0 TDI (Top view) Pin Arrangement (HM66AEB18204) 165PIN-BGA 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS DQ9 NC NC NC DQ12 NC VREF NC NC DQ15 NC NC NC TCK 3 SA NC NC DQ10 DQ11 NC DQ13 VDDQ NC DQ14 NC NC DQ16 DQ17 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 BW1 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K SA0 VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW0 SA1 VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC DQ7 NC NC NC NC VREF DQ4 NC NC DQ1 NC NC TMS 11 CQ DQ8 NC NC DQ6 DQ5 NC ZQ NC DQ3 DQ2 NC NC DQ0 TDI (Top view) Rev.0.0, Jan. 2003, page 3 of 30 HM66AEB36104/18204/9404 Pin Arrangement (HM66AEB9404) 165PIN-BGA 1 A B C D E F G H J K L M N P R CQ NC NC NC NC NC NC DOFF NC NC NC NC NC NC TDO 2 VSS NC NC NC NC NC NC VREF NC NC DQ6 NC NC NC TCK 3 SA NC NC NC DQ4 NC DQ5 VDDQ NC NC NC NC NC DQ7 SA 4 R/W SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 5 NC NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 6 K K NC VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C 7 NC BW SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA 8 LD SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA 9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA 10 SA NC NC NC NC NC NC VREF DQ1 NC NC NC NC NC TMS 11 CQ DQ3 NC NC DQ2 NC NC ZQ NC NC DQ0 NC NC DQ8 TDI (Top view) Note: Note that 7C is not SA1. The x9 product does not permit random start address on the two least significant address bits. SA0, SA1 = 0 at the start of each address. Rev.0.0, Jan. 2003, page 4 of 30 HM66AEB36104/18204/9404 Pin Descriptions Name SAn SA0 SA1 I/O type Descriptions Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. Ball 2A is reserved for the next higher-order address input on future devices. All transactions operate on burst-of-four words (two clock periods of bus activity). SA0 and SA1 are used as the lowest two address bits for burst READ and burst WRITE operations permitting a random burst start address on x18 and x36 devices. These inputs are ignored when device is deselected or once burst operation is in progress. Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ / WRITE direction. All transactions operate on a burst-of-four data (two clock periods of bus activity). Synchronous read / write Input: When LD is low, this input designates the access type (READ when R/W is high, WRITE when R/W is low) for the loaded address. R/W must meet the setup and hold times around the rising edge of K. Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K for each of the two rising edges comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K. K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of C is used as the output timing reference for second and fourth output data. The rising edge of C is used as the output reference for first and third output data. Ideally, C is 180 degrees out of phase with C. C and C may be tied high to force the use of K and K as the output reference clocks instead of having to provide C and C clocks. If tied high, C and C must remain high and not to be toggled during device operation. DLL disable: When low, this input causes the DLL to be bypassed for stable, lowfrequency operation. Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 x RQ, where RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left not connected if the JTAG function is not used in the circuit. IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. LD Input R/W Input BW BWn Input K, K Input C, C Input DOFF ZQ Input Input TMS TDI TCK Input Input Rev.0.0, Jan. 2003, page 5 of 30 HM66AEB36104/18204/9404 Name DQn I/O type Descriptions Input/ output Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and K. Output data is synchronized to the respective C and C data clocks, or to the respective K and K if C and C are tied high. The x9 device uses DQ0 to DQ8. Remaining signals are NC. The x18 device uses DQ0 to DQ17. Remaining signals are NC. The x36 device uses DQ0 to DQ35. NC signals are read in the JTAG scan chain as the logic level applied to the ball site. CQ, CQ Output Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tri-states. Output IEEE 1149.1 test output: 1.8 V I/O level. Supply Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Supply Power supply: Isolated output buffer supply. Nominally 1.5 V. 1.8 V is also permissible. See DC Characteristics and Operating Conditions for range. Supply Power supply: Ground HSTL input reference voltage: Nominally VDDQ/2. Provides a reference voltage for the input buffers. No connect: These signals are internally connected and appear in the JTAG scan chain as the logic level applied to the ball sites. These signals may be connected to ground to improve package heat dissipation. TDO VDD VDDQ VSS VREF NC Note: 1. All power supply and ground balls must be connected for proper operation of the device. Rev.0.0, Jan. 2003, page 6 of 30 HM66AEB36104/18204/9404 Block Diagram (HM66AEB36104) SA1 SA0 20 Address Registry & Logic SA1' SA0' SA0'' Output SA0''' Control Logic Burst Logic SA 20 LD R/W K LD BW0 BW1 BW2 BW3 K R/W WRITE Register Output Register 2 36 WRITE Driver Output Buffer Output Select Sense Amps Data Registry & Logic 36 CQ, CQ DQ0-35 72 K Memory Array MUX 72 C 72 K C, C or K, K Block Diagram (HM66AEB18204) SA1 SA0 21 Address Registry & Logic SA1' SA0' SA0'' Output SA0''' Control Logic Burst Logic SA 21 LD R/W K R/W WRITE Register Output Register LD BW0 BW1 K 2 18 WRITE Driver Output Buffer Output Select Sense Amps Data Registry & Logic 18 CQ, CQ DQ0-17 36 K Memory Array MUX 36 C 36 K C, C or K, K Rev.0.0, Jan. 2003, page 7 of 30 HM66AEB36104/18204/9404 Block Diagram (HM66AEB9404) SA 20 Address Registry 20 & Logic LD R/W K R/W LD BW K WRITE Register Output Register 2 9 WRITE Driver Output Buffer Output Select Data Registry & Logic 9 CQ, CQ DQ0-8 Sense Amps 18 K Memory Array MUX 18 C 18 K C, C or K, K Rev.0.0, Jan. 2003, page 8 of 30 HM66AEB36104/18204/9404 Burst Sequence Linear Burst Sequence Table (HM66AEB36104/18204) SA1, SA0 External address 1st internal burst address 2nd internal burst address 3rd internal burst address 0, 0 0, 1 1, 0 1, 1 SA1, SA0 0, 1 1, 0 1, 1 0, 0 SA1, SA0 1, 0 1, 1 0, 0 0, 1 SA1, SA0 1, 1 0, 0 0, 1 1, 0 Truth Table Operation WRITE cycle Load address, input write data on two consecutive K and K rising edges K LH LD L R/W W L DQ Data in Input data Input clock LH L H Data out Output QA(A+0) data Output C(t+1) clock LH H x x x High-Z Previous state QA(A+1) C(t+2) QA(A+2) C(t+2) QA(A+3) C(t+3) DA(A+0) K(t+1) DA(A+1) K(t+1) DA(A+2) K(t+2) DA(A+3) K(t+2) READ cycle Load address, read data on two consecutive C and C rising edges NOP (No operation) Notes: 1. 2. 3. 4. 5. 6. 7. STANDBY (Clock stopped) Stopped H: high level, L: low level, x: don't care, : rising edge. Data inputs are registered at K and K rising edges. Data outputs are delivered at C and C rising edges, except if C and C are high, then data outputs are delivered at K and K rising edges. All control inputs in the truth table must meet setup/hold times around the rising edges (low to high) of K. ALL control inputs are registered during the rising edge of K. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. Refer to state diagram and timing diagrams for clarification. It is recommended that (K) = /(K) = (C) = /(C) when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. "A+0" refers to the address input during a WRITE or READ cycle. "A+1", "A+2" and "A+3" refer to the internal burst address in accordance with the linear burst sequence. Rev.0.0, Jan. 2003, page 9 of 30 HM66AEB36104/18204/9404 Byte Write Truth Table (HM66AEB36104) Operation Write D0 to D35 K LH Write D0 to D8 LH Write D9 to D17 LH Write D18 to D26 LH Write D27 to D35 LH Write nothing LH K LH LH LH LH LH LH BW0 0 0 0 0 1 1 1 1 1 1 1 1 BW1 0 0 1 1 0 0 1 1 1 1 1 1 BW2 0 0 1 1 1 1 0 0 1 1 1 1 BW3 0 0 1 1 1 1 1 1 0 0 1 1 Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 to BW3 can be altered for any portion of the burst WRITE operation provided that the setup and hold requirements are satisfied. (HM66AEB18204) Operation Write D0 to D17 K LH Write D0 to D8 LH Write D9 to D17 LH Write nothing LH K LH LH LH LH BW0 0 0 0 0 1 1 1 1 BW1 0 0 1 1 0 0 1 1 Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW0 and BW1 can be altered for any portion of the burst WRITE operation provided that the setup and hold requirements are satisfied. Rev.0.0, Jan. 2003, page 10 of 30 HM66AEB36104/18204/9404 (HM66AEB9404) Operation Write D0 to D8 K LH Write nothing LH K LH LH BW 0 0 1 1 Notes: 1. H: high level, L: low level, : rising edge. 2. Assumes a WRITE cycle was initiated. BW can be altered for any portion of the burst WRITE operation provided that the setup and hold requirements are satisfied. Bus Cycle State Diagram LD = L LD = H, Count = 4 Count = 2 Count = 4 LD = L, WRITE DOUBLE Count = Count + 2 Always ADVANCE ADDRESS BY TWO R/W = L LOAD NEW ADDRESS Count = 0 R/W = H Count = 2 LD = H NOP LD = L, Count = 4 READ DOUBLE Count = Count + 2 Always ADVANCE ADDRESS BY TWO Supply voltage provided LD = H, Count = 4 POWER UP Notes: 1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst count = 4. 2. State machine control timing sequence is controlled by K. Rev.0.0, Jan. 2003, page 11 of 30 HM66AEB36104/18204/9404 Absolute Maximum Ratings Parameter Input voltage on any ball Input/output voltage Core supply voltage Output supply voltage Junction temperature Storage temperature Symbol VIN VI/O VDD VDDQ Tj TSTG Rating -0.5 to VDD + 0.5 (2.9 V max.) -0.5 to VDDQ + 0.5 (2.9 V max.) -0.5 to 2.9 -0.5 to VDD +125 (max) -55 to +125 Unit V V V V C C Notes 1, 4 1, 4 1, 4 1, 4 Notes: 1. All voltage is referenced to VSS. 2. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation should be restricted the Operation Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. 3. These CMOS memory circuits have been designed to meet the DC and AC specifications shown in the tables after thermal equilibrium has been established. 4. The following supply voltage application sequence is recommended: VSS, VDD, VDDQ, VREF then VIN. Remember, according to the Absolute Maximum Ratings table, VDDQ is not to exceed 2.9V, whatever the instantaneous value of VDDQ. Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Power supply voltage -- core Power supply voltage -- I/O Input reference voltage -- I/O Input high voltage Input low voltage Symbol VDD VDDQ VREF VIH (DC) VIL (DC) Min 1.7 1.4 0.68 VREF + 0.1 -0.3 Typ 1.8 1.5 0.75 Max 1.9 VDD 0.95 VDDQ + 0.3 VREF - 0.1 Unit V V V V V 1 2, 3 2, 3 Notes Notes: 1. Peak to peak AC component superimposed on VREF may not exceed 5% of VREF. 2. VREF = 0.75 V (typ). 3. Overshoot: VIH (AC) VDD + 0.7 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). Rev.0.0, Jan. 2003, page 12 of 30 HM66AEB36104/18204/9404 DC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V) HM66AEB36104/HM66AEB18204 HM66AEB9404 -30 Parameter Operating supply current (READ / WRITE) Symbol Typ Max -33 -40 -50 -60 Unit Notes (x9 / x18) IDD (x36) IDD TBD 390 TBD 520 355 475 300 400 250 330 215 285 mA mA Standby supply current (NOP) (x9 / x18) ISB1 (x36) ISB1 TBD 255 TBD 265 235 245 200 210 170 180 150 160 mA mA Notes 1. 2. 3. 4. 5. All inputs (except ZQ, VREF) are held at either VIH or VIL. IOUT = 0 mA. VDD = VDD max, tKHKH = tKHKH min. Typical values are measured at VDD = 1.8 V, VDDQ = 1.5 V, Ta = +25C, and tKHKH = 6 ns. Operating supply currents are measured at 100% bus utilization. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. Parameter Input leakage current Symbol Min ILI VOH (Low) VOH -2 -2 VDDQ - 0.2 VDDQ/2 - 0.08 VSS VDDQ/2 - 0.08 Max 2 2 VDDQ VDDQ/2 + 0.08 0.2 VDDQ/2 + 0.08 Unit Test conditions Notes A A V V V V |IOH| 0.1 mA Notes1 IOL 0.1 mA Notes2 8 9 3, 4 3, 4 3, 4 3, 4 5, 7 6, 7 Output leakage current ILO Output high voltage Output low voltage VOL (Low) VOL Output "High" current Output "Low" current IOH IOL (VDDQ/2)/(RQ/5 + 10%) (VDDQ/2)/(RQ/5 - 10%) mA (VDDQ/2)/(RQ/5 - 10%) (VDDQ/2)/(RQ/5 + 10%) mA Rev.0.0, Jan. 2003, page 13 of 30 HM66AEB36104/18204/9404 Notes: 1. 2. 3. 4. 5. 6. 7. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 RQ 350 . AC load current is higher than the shown DC values. AC I/O curves are available upon request. HSTL outputs meet JEDEC HSTL Class I and Class II standards. Measured at VOH = VDDQ/2 Measured at VOL = VDDQ/2 Output buffer impedance can be programmed by terminating the ZQ ball to VSS through a precision resistor (RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to guarantee impedance matching with a tolerance of 10% is 250 typical. The total external capacitance of ZQ ball must be less than 7.5 pF. 8. 0 VIN VDDQ for all input balls (except ZQ ball) 9. 0 VOUT VDDQ, output disabled. 10. VDDQ = 1.5 V 0.1 V Capacitance (Ta = +25C, f = 1.0 MHz, VDD = 1.8 V) Parameter Input capacitance Clock input capacitance Input/output capacitance (DQ) Symbol CIN CCLK CI/O Min Typ 4 5 6 Max 5 6 7 Unit pF pF pF Test conditions VIN = 0 V VCLK = 0 V VI/O = 0 V Notes: 1. These parameters are sampled and not 100% tested. 2. Parameters tested with RQ = 250 and VDDQ = 1.5 V. Rev.0.0, Jan. 2003, page 14 of 30 HM66AEB36104/18204/9404 AC Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V) Test Conditions Input waveform (Rise/fall time 0.3 ns) 1.25 V 0.75 V 0.25 V Test points 0.75 V Output waveform VDDQ/2 Test points VDDQ/2 Output load condition 0.75 V VREF 16.7 SRAM DQ 250 ZQ 16.7 50 50 0.75 V 16.7 50 50 0.75 V 0.75 V Rev.0.0, Jan. 2003, page 15 of 30 HM66AEB36104/18204/9404 Operating Conditions Parameter Input high voltage Input low voltage Notes: 1. 2. Symbol VIH (AC) VIL (AC) Min VREF + 0.2 Typ Max VREF - 0.2 Unit V V Notes 1, 2, 3 1, 2, 3 3. All voltages referenced to VSS (GND). Overshoot: VIH (AC) VDD + 0.7 V for t tKHKH/2 Undershoot: VIL (AC) -0.5 V for t tKHKH/2 Power-up: VIH VDDQ + 0.3 V and VDD 1.7 V and VDDQ 1.4 V for t 200 ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (min) or operate at cycle rates less than tKHKH (min). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC). Rev.0.0, Jan. 2003, page 16 of 30 HM66AEB36104/18204/9404 HM66AEB36104/HM66AEB18204 HM66AEB9404 -30 Parameter Symbol Min 3.00 Max 3.47 -33 Min 3.30 Max 4.20 -40 Min 4.00 Max 5.25 -50 Min 5.00 Max 6.30 -60 Min 6.00 Max 7.88 Unit Notes ns Average clock tKHKH cycle time (K, K, C, C) Clock phase jitter (K, K, C, C) tKC var 0.20 0.20 0.20 0.20 0.20 ns 3 Clock high time tKHKL (K, K, C, C) Clock low time tKLKH (K, K, C, C) Clock to clock tKH/KH (K to K, C to C) Clock to clock t/KHKH (K to K, C to C) Clock to data tKHCH clock (K to C, K to C) DLL lock time (K, C) 1.20 1.20 1.35 1.35 0 1.30 1.32 1.32 1.49 1.49 0 1.45 1.60 1.60 1.80 1.80 0 1.80 2.00 2.00 2.20 2.20 0 2.30 2.40 2.40 2.70 2.70 0 2.80 ns ns ns ns ns tKC lock 1,024 0.45 1,024 30 0.45 1,024 30 0.45 1,024 30 0.45 1,024 30 0.50 Cycle 2 ns ns ns ns K static to DLL tKC reset 30 reset C, C high to output valid C, C high to output hold C, C high to echo clock valid tCHQV tCHQX tCHCQV -0.45 0.45 -0.45 0.45 -0.45 0.45 -0.45 0.45 -0.50 0.50 C, C high to tCHCQX echo clock hold CQ, CQ high to tCQHQV output valid CQ, CQ high to tCQHQX output hold C high to output high-Z C high to output low-Z tCHQZ tCHQX1 -0.45 0.25 -0.45 0.27 -0.45 0.30 -0.45 0.35 -0.50 0.40 ns ns ns ns ns 4 4 5 5 -0.25 0.45 -0.27 0.45 -0.30 0.45 -0.35 0.45 -0.40 0.50 -0.45 -0.45 -0.45 -0.45 -0.50 Rev.0.0, Jan. 2003, page 17 of 30 HM66AEB36104/18204/9404 HM66AEB36104/HM66AEB18204 HM66AEB9404 -30 Parameter Symbol Min 0.40 0.40 Max -33 Min 0.40 0.40 Max -40 Min 0.50 0.50 Max -50 Min 0.60 0.60 Max -60 Min 0.70 0.70 Max Unit Notes ns ns 1 1 Address valid tAVKH to K rising edge Control inputs tIVKH valid to K rising edge Data-in valid to tDVKH K, K rising edge K rising edge to tKHAX address hold K rising edge to tKHIX control inputs hold tKHDX K, K rising edge to data-in hold 0.28 0.30 0.35 0.40 0.50 ns 1 0.40 0.40 0.40 0.40 0.50 0.50 0.60 0.60 0.70 0.70 ns ns 1 1 0.28 0.30 0.35 0.40 0.50 ns 1 Notes: 1. This is a synchronous device. All addresses, data and control lines must meet the specified setup and hold times for all latching clock edges. 2. VDD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. It is recommended that the device is kept inactive during these cycles. 3. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 4. Echo clock is very tightly controlled to data valid / data hold. By design, there is a 0.1 ns variation from echo clock to data. The datasheet parameters reflect tester guardbands and test setup variations. 5. Transitions are measured 100 mV from steady-state voltage. 6. At any given voltage and temperature tCHQZ is less than tCHQX1 and tCHQZ less than tCHQV. Remarks: 1. This parameter is sampled. 2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise noted. 3. Control input signals may not be operated with pulse widths less than tKHKL (min). 4. If C, C are tied high, K, K become the references for C, C timing parameters. 5. VDDQ is +1.5 V DC. Rev.0.0, Jan. 2003, page 18 of 30 HM66AEB36104/18204/9404 Timing Waveforms Read and Write Timing NOP READ (burst of 4) READ (burst of 4) NOP NOP WRITE (burst of 4) WRITE (burst of 4) READ (burst of 4) 1 K 2 tKHKH 3 4 5 6 7 8 9 10 11 12 13 tKHKL tKLKH tKH/KH t/KHKH K LD tIVKH R/W tAVKH tKHAX SA A0 A1 A2 A3 A4 tKHIX DQ tKHDX tDVKH Qx2 Q01 Q02 Q03 Q04 Q11 Q12 Q13 Q14 D21 tKHDX tDVKH D22 D23 D24 D31 D32 D33 D34 Q41 tKHCH CQ tCHCQX1 tKHCH tCHQV tCHQX tCHQV tCHQX tCQHQV tCQHQX tCHQZ CQ C tCHCQX tCHCQV tCHCQX tCHCQV C tKHKLtKLKH tKHKH tKH/KH t/KHKH Notes: 1. Q01 refers to output from address A0. Q02 refers to output from the next internal burst address following A0, etc. 2. Outputs are disable (high-Z) one clock cycle after a NOP. 3. The second NOP cycle is not necessary for correct device operation; however, at high clock frequencies it may be required to prevent bus contention. Rev.0.0, Jan. 2003, page 19 of 30 HM66AEB36104/18204/9404 JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Disabling the Test Access Port It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfering with normal operation of the device, TCK must be tied to VSS to preclude mid level inputs. TDI and TMS are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected. But they may also be tied to VDD through a 1k resistor. TDO should be left unconnected. Test Access Port (TAP) Pins Symbol I/O TCK TMS TDI Pin assignments 2R 10R 11R Description Test clock input. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. Test mode select. This is the command input for the TAP controller state machine. Test data input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction. Test data output. Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. TDO 1R Note: The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held high for five rising edges of TCK. The TAP controller state is also reset on SRAM POWER-UP. Rev.0.0, Jan. 2003, page 20 of 30 HM66AEB36104/18204/9404 TAP DC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V) Parameter Input high voltage Input low voltage Input leakage current Output leakage current Output low voltage Symbol VIH VIL ILI ILO VOL1 VOL2 Output high voltage VOH1 VOH2 Min 1.3 -0.3 -5.0 -5.0 1.6 1.4 Max VDD + 0.3 +0.5 +5.0 +5.0 0.2 0.4 Unit V V A A V V V V 0 V VIN VDD 0 V VIN VDD, output disabled IOLC = 100 A IOLT = 2 mA |IOHC| = 100 A |IOHT| = 2 mA Conditions Notes: 1. All voltages referenced to VSS (GND). 2. Power-up: VIH VDDQ + 0.3 V and VDD +1.7 V and VDDQ +1.4 V for t 200 ms 3. In "EXTEST" mode and "SAMPLE" mode, VDDQ is nominally 1.5 V. Rev.0.0, Jan. 2003, page 21 of 30 HM66AEB36104/18204/9404 TAP AC Test Condition * Temperature * Input timing measurement reference levels * Input pulse levels * Input rise/fall time * Output timing measurement reference levels * Test load termination supply voltage (VTT) * Output load Input waveform 1.8 V 0.9 V 0V Test points 0.9 V 0C Ta +70C 0.9 V 0 V to 1.8 V 1.0 ns 0.9 V 0.9 V See figures Output waveform 0.9 V Test points 0.9 V Output load VTT = 0.9 V 50 Zo = 50 TDO 20 pF External load at test Rev.0.0, Jan. 2003, page 22 of 30 HM66AEB36104/18204/9404 TAP AC Operating Characteristics (Ta = 0 to +70C, VDD = 1.8 V 0.1 V) Parameter Test clock cycle time Test clock high pulse width Test clock low pulse width Test mode select setup Test mode select hold Capture setup Capture hold TDI valid to TCK high TCK high to TDI invalid TCK low to TDO unknown TCK low to TDO valid Note: Symbol tTHTH tTHTL tTLTH tMVTH tTHMX tCS tCH tDVTH tTHDX tTLQX tTLQV Min 100 40 40 10 10 10 10 10 10 0 Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns 1 1 Note 1. tCS + tCH defines the minimum pause in RAM I/O pad transitions to assure pad data capture. TAP Controller Timing Diagram tTHTH TCK tMVTH TMS tTHMX TDI tTHDX TDO tCS RAM ADDRESS tCH tTLQX tTLQV tDVTH tTHTL tTLTH Test Access Port Registers Register name Instruction register Bypass register ID register Boundary scan register Length 3 bits 1 bit 32 bits 109 bits Symbol IR [2:0] BP ID [31:0] BS [109:1] Rev.0.0, Jan. 2003, page 23 of 30 HM66AEB36104/18204/9404 TAP Controller Instruction Set IR2 0 IR1 0 IR0 0 Instruction EXTEST Description The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output balls. The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO balls in shiftDR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z, except CQ, CQ ball) and the boundary register is connected between TDI and TDO when the TAP controller is moved to the shift-DR state. These instructions are not implemented but are reserved for future use. Do not use these instructions. When the SAMPLE instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to SAMPLE metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO balls. Notes 1, 2 0 0 1 IDCODE 0 1 0 SAMPLE-Z 0 1 1 0 1 0 RESERVED SAMPLE (-PRELOAD) 1 1 1 0 1 1 1 0 1 RESERVED RESERVED BYPASS The BYPASS instruction is loaded in the instruction register when the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Notes: 1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation. Rev.0.0, Jan. 2003, page 24 of 30 HM66AEB36104/18204/9404 ID Register Part HM66AEB36104 HM66AEB18204 HM66AEB9404 Revision number (31:29) 000 000 000 Type number (28:12) 00010011010001000 00010010010001000 00010000010001000 Vendor JEDEC code (11:1) 00000000111 00000000111 00000000111 Start bit (0) 1 1 1 Rev.0.0, Jan. 2003, page 25 of 30 HM66AEB36104/18204/9404 Boundary Scan Order Signal names Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Ball ID 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E x9 C C SA SA SA SA SA SA SA DQ8 NC NC NC NC NC NC NC DQ0 NC NC NC NC NC NC NC DQ1 NC ZQ NC NC NC NC NC NC DQ2 x18 C C SA SA SA SA SA SA SA DQ0 NC NC NC DQ1 NC NC NC DQ2 NC NC NC DQ3 NC NC NC DQ4 NC ZQ NC NC DQ5 NC NC NC DQ6 x36 C C SA SA SA SA SA SA SA DQ0 DQ9 NC NC DQ11 DQ10 NC NC DQ2 DQ1 NC NC DQ3 DQ12 NC NC DQ13 DQ4 ZQ NC NC DQ5 DQ14 NC NC DQ6 Bit # 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Ball ID 10E 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D Signal names x9 NC NC NC NC NC NC NC DQ3 NC NC NC CQ SA SA SA SA NC LD NC BW K K NC NC R/W SA SA SA VSS CQ NC NC NC NC NC x18 NC NC NC DQ7 NC NC NC DQ8 NC NC NC CQ SA SA SA SA1 SA0 LD NC BW0 K K NC BW1 R/W SA SA SA VSS CQ DQ9 NC NC NC DQ10 x36 DQ15 NC NC DQ17 DQ16 NC NC DQ8 DQ7 NC NC CQ NC SA SA SA1 SA0 LD BW1 BW0 K K BW3 BW2 R/W SA SA SA VSS CQ DQ27 DQ18 NC NC DQ19 Rev.0.0, Jan. 2003, page 26 of 30 HM66AEB36104/18204/9404 Signal names Bit # 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 Ball ID 3C 1D 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K x9 NC NC NC DQ4 NC NC NC NC NC NC NC DQ5 NC DOFF NC NC NC NC NC x18 NC NC NC DQ11 NC NC NC DQ12 NC NC NC DQ13 NC DOFF NC NC DQ14 NC NC x36 DQ28 NC NC DQ20 DQ29 NC NC DQ30 DQ21 NC NC DQ22 DQ31 DOFF NC NC DQ23 DQ32 NC Bit # 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 Ball ID 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R Signal names x9 DQ6 NC NC NC NC NC NC NC DQ7 NC NC NC SA SA SA SA SA SA INTERNAL x18 DQ15 NC NC NC DQ16 NC NC NC DQ17 NC NC NC SA SA SA SA SA SA INTERNAL x36 DQ33 DQ24 NC NC DQ25 DQ34 NC NC DQ26 DQ35 NC NC SA SA SA SA SA SA INTERNAL 90 1K NC NC NC Note: In boundary scan mode, 1. Clock balls (K / K, C / C) are referenced to each other and must be at opposite logic levels for reliable operation. 2. CQ and CQ data are synchronized to the respective C and C. 3. If C and C tied high, CQ is generated with respect to K and CQ is generated with respect to K. Rev.0.0, Jan. 2003, page 27 of 30 HM66AEB36104/18204/9404 TAP Controller State Diagram 1 Test-LogicReset 0 0 Run-Test/ Idle 1 SelectDR-Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 1 SelectIR-Scan 0 1 Capture-IR 0 0 Shift-IR 1 1 0 1 1 Exit1-IR 0 0 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 Notes: The value adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK. No matter what the original state of the controller, it will enter Test-Logic-Reset when TMS is held high for at least five rising edges of TCK. Rev.0.0, Jan. 2003, page 28 of 30 HM66AEB36104/18204/9404 Package Dimensions HM66AEB36104/18204/9404BP (BP-165A) Preliminary Unit: mm 15.00 0.20 14 x 1.00 165 x 0.50 0.05 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R 10 x 1.00 17.00 0.20 0.25 C C 0.40 0.06 0.10 C 1.44 0.10 Hitachi Code JEDEC JEITA Mass (reference value) BP-165A - - - Rev.0.0, Jan. 2003, page 29 of 30 HM66AEB36104/18204/9404 Disclaimer 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Sales Offices Hitachi, Ltd. Semiconductor & Integrated Circuits Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: (03) 3270-2111 Fax: (03) 3270-5109 URL http://www.hitachisemiconductor.com/ For further information write to: Hitachi Semiconductor (America) Inc. 179 East Tasman Drive San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223 Hitachi Europe Ltd. Electronic Components Group Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Europe GmbH Electronic Components Group Dornacher Str 3 D-85622 Feldkirchen Postfach 201, D-85619 Feldkirchen Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Asia Ltd. Hitachi Tower 16 Collyer Quay #20-00 Singapore 049318 Tel : <65>-6538-6533/6538-8577 Fax : <65>-6538-6933/6538-3877 URL : http://semiconductor.hitachi.com.sg Hitachi Asia Ltd. (Taipei Branch Office) 4/F, No. 167, Tun Hwa North Road Hung-Kuo Building Taipei (105), Taiwan Tel : <886>-(2)-2718-3666 Fax : <886>-(2)-2718-8180 Telex : 23222 HAS-TP URL : http://semiconductor.hitachi.com.tw Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel : <852>-2735-9218 Fax : <852>-2730-0281 URL : http://semiconductor.hitachi.com.hk Copyright (c) Hitachi, Ltd., 2002. All rights reserved. Printed in Japan. Colophon 7.0 Rev.0.0, Jan. 2003, page 30 of 30 |
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